MIPI homepage CMOS prescaler basics
Circuit configuration of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure
adding reset function to D Flip FLOP | Forum for Electronics
Help me calculate the device size of CML/SCL latch design and simulate the gain of it | Forum for Electronics
4-bit Counter Using High-Speed Low-Voltage CML D-Flipflops | Semantic Scholar
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
Figure 1 from A 45 mW RTD/HBT MOBILE D-Flip Flop IC Operating up to 32 Gb/s | Semantic Scholar
adding reset function to D Flip FLOP | Forum for Electronics
Electronics | Free Full-Text | 40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors
Figure 5.21 from Cmos Logic and Current Mode Logic 5.1 Introduction | Semantic Scholar
A Novel Ultra High-Speed Flip-Flop-Based Frequency Divider: Ravindran Mohanavelu and Payam Heydari | PDF
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
Circuit configuration of the RTD/HBT MOBILE-based NRZ D-flip flop. | Download Scientific Diagram
Schematic timing diagram of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
High Speed Digital Blocks
An improved current mode logic latch for high‐speed applications
Asynchronous Primitives in CML - ppt download
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
CML based DFF used in 4/5 prescaler block | Download Scientific Diagram
Figure 16.23 from Direct-coupled Fet Logic (dcfl) @bullet Source-coupled Fet Logic (scfl) @bullet Advanced Mesfet/hemt Design Examples Iii-v Hbt for Circuit Designers @bullet Current-mode Logic @bullet Emitter-coupled Logic @bullet Ecl/cml Logic Examples @
Current Mode Logic Divider
A Dynamic Current Mode D-Flipflop for High Speed Application | Semantic Scholar
Performance evaluation of the low-voltage CML D-latch topology - ScienceDirect
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
ECEN620: Network Theory Broadband Circuit Design Fall 2022
